1. Field of the Invention
The present invention is related to Integrated Circuits and, more particularly, to shift register latches used in integrated circuits.
2. Background Description
Integrated Circuit (IC) chip performance is determined by its critical path, i.e., the logic path with the longest propagation delay. Level sensitive scan design (LSSD) and other synchronous architectures have shift register latches at various stages in chip logic paths to shorten the critical paths, allowing the chips to operate at higher clock speeds.
FIG. 1 is a schematic of a prior art LSSD latch 50, which is, typically, a two stage latch that includes a first stage, called the "L1" stage or latch and a second stage called the "L2" stage or latch. The L1 stage includes a first latch 52 and a pair of input clock stages 54, 56, that, preferably, are identical. The first stage also includes input buffers 58, 60 buffering input data signals D0, I0, respectively. The output of the L1 latch 52 is buffered by inverter 62 for stability. The L2 stage includes a clock stage 64, a latch 66 and an output buffer 68 in parallel with the L2 latch 66.
Normally, data is received by and clocked into the L1 latch 52, passed from the L1 latch 52 to the L2 latch 66 and clocked out of the L2 latch 66. The LSSD latch stage delay includes the L1 latch 52 setup time, L1 latch 52 settling time, the L2 latch 66 setup time and the propagation delay through the L2 latch 66, i.e., the delay between asserting the L2 latch clock (B)) and having valid data at the output 68 of the L2 buffer. These LSSD latch delays may be equivalent to the delay of multiple logic stages. Consequently, the shorter the logic path between LSSD stages, the more dominant the latch stage delay itself becomes.
Thus, there is a need for reducing LSSD latch propagation delays.